Solid-state traffic controller

ABSTRACT

A controller for traffic lights employing solid-state components and providing both vehicular and pedestrian control. Cross street controls initiate operation of a binary counter sequentially to operate signal lights through predetermined time intervals. Interconnecting circuits provide for coordination with other signal lights, vehicle extension intervals, recall and resetting controls. An auxiliary memory circuit operates to distinguish between vehicle only and pedestrian operation.

United States Patent Inventor Philip Cane I Brooklyn, N.Y. Appl. No.702,912 Filed Jan. 31, I968 Patented July 20, I971 Assignee TheMarbelitc Company, Inc.

Brooklyn, N.Y.

SOLID-STATE TRAFFIC CONTROLLER 9 Claims 6 Drawing Figs control. Crossstreet controls initiate operation of a binary US. Cl 340/44, un ersequentially to operate signal lights through predeter- 340/ 37 minedtime intervals. Interconnecting circuits provide for Int. Cl G08g 1/09,coordination with other signal lights, vehicle extension inter- G08 1/08vals, recall and resetting controls. An auxiliary memory circuit Fieldof Search 340/44, 35, operates to distinguish between vehicle only andpedestrian 37 operation.

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rmutuomr FED-lilo" [56] References Cited UNITED STATES PATENTS PrimaryExaminer-Thomas B. Habecker Attorney-Wolf, Greenfield & Sacks ABSTRACT:A controller for traffic lights employing solidstate components andproviding both vehicular and pedestrian mmivu.

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YELLOW R DWK| Y2 owx I I o l ALL RED R owK R I wI o o I I L E G EN DG.,Y,, R PHASE "A" GREEN ,IYELLOW, RED SIGNALS RESPECTIVELY. e ,Y2, R2-PHASE'B" GREEN YELLOW, RED SIGNALS RESPECTIVELY.

wI ,FLowK,,owI PHASE'W'WALK, FLASHING 00m WALK, 00m WALK RESPECTIVELY-MR ,FLDWK2,DWK2-PHASE'B"WALK, FLASHING 00m WALK, 00m WALK RESPECTIVELY-INVENTOR PHILIP CANE TTOR SOLID-STATE TRAFFIC CONTROLLER This inventionrelates to traffic control signal systems and more particularly tocontrollers actuated by vehicles and/or pedestrians. 1

When a cross street intersects a main street, it is desirable to arrangethe controller so that the main street lights will stay green until avehicle approaches on a cross street and thereupon to actuate the crossstreet lights to green, the main street lights turning to red.

Also, when pedestrians approach, it is desirable'to be able to changethe lights so that the main street can be crossed.

Prior devices have not been completely satisfactory, particularly thosewhere complicated mechanical movements are involved. It is desirable tobe able to use solid-state actuated arrangements in a simplified mannerfor the actuation and control of trafi'rc signals. Also, it is necessaryin a traffic control system to have dependability along with simplicity.

One of the objects of the invention is to use standard, readilyavailable electronic components which are mass-produced and which may bereadily applied to the present invention.

Another of the objects of the invention is to provide a traffic controlsystem whichis relatively simple and dependable.

Hereafter, the main street will be referred to as "A," some timesreferred to as l," and the cross street as "phase B," sometimes referredto as 2." The controller is arrangedto provide intervals in which therewill be a phase A minimum period, a phase A rest period, a phase Apedestrian clearance period, a phase A yellow period, and an all-redperiod which can be identified as a phase A all-red. The latter meansthat the signals are red in all directions.

in the operation of the phase B portion, there will be a phase B initialperiod which is broken into two subdivisions known as initial 1" andinitial ll." There will also be a phase B extension, a phase B yellow,and a phase B all-red" period.

Extension, in the art, means that the green period is flexible in lengthand may be present within certain limits, but the actual green time iscontrolled in some manner by the passage of vehicles. Recall, in theart, means the automatic return to the phase A green in spite of thefact that additional vehicles are present on the cross street.

To accommodate pedestrian traffic, there can be interposed a Walkperiod, phase B Initial I," followed by a pedestrian clearance period,phase B Initial ll, such being activated by pedestrian control buttons.When actuated by vehicles only, 8 Initial l" and Initial ll" go into twosuccessive intervals of green and Don't Walk."

These and other objects, advantages and features of the invention willbecome apparent from the following description and accompanying drawingswhich are merely exemplary.

in the drawings:

FIG. 1 shows a block diagram of one form of the invention;

FIGS. 2A, 2B, 2C and 2D show a specific circuit arrangement for one fonnof the invention; and

FIG. 3 is a tabulation showing the relationship between the controllerintervals, the signal indications and the outputs of I the controllercounter.

Referring now to the block diagram of FIG. 1, phase A of the main streetlight is normally green and the counter at A" rest position, havingpassed through a green minimum period. When a vehicle approaches on across street, however, it will operate a vehicle detector indicatedgenerally by the box and cause operation of a vehicle memory'circuitindicated by box 12. In like manner, if a pedestrian desires to crossthe main street, a pedestrian control pushbutton indicated by box 1] isprovided and operates a pedestrian memory circuit indicated by the box13. The output of the vehicle memory or the pedestrian memory circuitsis fed to an and" circuit indicated by box 14. if other circuitconditions are right, this will cause a stepping voltage or signal tothe timing circuits indicated generally by the box 15. These circuitsare also fed by an interval timing input'and a maximum timing input fedfrom the timing potentiometers of box l9.

The timing circuits provide a trigger voltage which functions toposition an electronic counter, which in the illustrated embodiment is abinary-type counter indicated by box 16. It is to be understood thatother types of counters can be used. Counter vl6 may be a four-stagebinary counter which has been designed to operate-through a total of IOpositions. The outputs of the binary counter are fed to interval gatecircuits denoted generally by box 17. The interval gates of box 17 arealso provided with a signal derived from the pedestrian memory circuitfor a purpose hereinafter to be described. The outputs of the gatecircuits control relay drivers, box 18, which operate a relay matrixillustrated by box 20. The relay matrix, in turn, controls sequencing ofthe signal lights schematically shown in box 21. The relay matrix of box20 may be solid-state devices or may be electromechanical devices ofvarious types. An output from the relay drivers 18 also feeds the timingpotentiometers of box 19. Outputs from the timing potentiometers are fedbackto the timing circuits included in box 15 and cooperate with thetiming circuits to provide for controllable, variable, individual timingof each of the circuits needed for control purposes.

The overall operation of the control device will be best understood byreference again to the block diagramot FIG. I. The controller isessentially a sequential device'in which sets of traffic lights, box 2]are displayed for controllable intervals of time. The relay matrix, box20, controls the power circuits for the lights of box 2]. The relaymatrix, in this case of a solid-state type, is driven by the relaydrivers, box 18, which are essentially solid-state amplifying devices tobring the signal level up to a sufficient value to operate the relaydevices inthe matrix 20.

The relay drivers which control the relay matrix are, in turn,controlled by the solid-state interval gate devices or circuits of box17. The interval gates control the relay drivers so that, in spite ofthe many intervals which are necessary for proper operation of thecontroller, the motorist and pedestrian see only the light sequence, notthe subdivisions of the light sequence. Thus, for example, there may beseveral intervals during which Green-l is displayed. This taken up morecompletely in terms of signal indications and interval relation- 1 shipsin PK]. 3.

The interval gates provide a solid-state static mechanism whereby theoutputs from the binary'counter, box 16, are translated by means oftypical and" gates into specific and discrete interval signals. Theinterval gates are also controlled by the pedestrian auxiliary memorycircuit. This circuit, in conjunction with the counter output,determines specifically whether the controller will operate to providephase B initial intervals I and ll for a vehicle call only, or thepedestrian intervals (Initial 1) Walk and (Initial ll) PedestrianClearance which are provided in the event of a pedestrian call with orwithout a vehicle call.

The counter is a binary electronic counter which changes condition atthe reception of a pulse, that is, each pulse changes the counter intoits next stage, and returns it to a first position at the pulse thattakes place in the last position. The count pulse is derived from theoutput of the timing circuits. This pulse is not repetitive but comes ata time that is determined by means of the timing potentiometers of box19. That is, the space between pulses is variable to a large extent andis predetermined by controls which are preset by the consumer, in thiscase, the traffic engineer or his deputy.

While the controller has been referred to as sequential, it is nottotally sequential but depends upon the nature of the traffic flow. Forexample, if there is no traffic flow in the secondary street and ifthere are no pedestrians who wish to cross the main street, then thecontroller output, namely, the counter 16, the interval gates 17, therelay drivers 18 and the relay matrix 20, will react to provide signallights 21 which indicate Green-l or right-of-way for the main street,and Red-2" which is stop for the cross street. At the same time, fWalk-lon the main street light will indicate that it is safe for pedestriansto cross the cross street while "Don't Wulk2 warns against crossing themain street. These signals will remain until such time as there is somekind ofvehicular or pedestrian need to change the condition. In thisevent, either the vehicle detector of box or the pedestrian pushbuttonof box 11 may be utilized to operate the vehicle memory circuit 12and/or the pedestrian memory circuits 13. This circuitry, otherconditions being satisfactory, starts the counter of box 16 from itsRest" position so that a sequence such as shown in FIG. 3 is possible.

Ordinarily, the counter remains in the "Rest" position with the signalindications as shown in FIG. 3. This counter can be started, however, bysignals from the vehicle and/or the pedestrian memory circuits which arefed to the and" circuit of box 14 and provide a voltage which isimpinged upon a very rapid timing circuit included in box 15. This rapidtiming circuit provides a pulse which drives the counter into the A-Pedestrian Clearance" position, i.e., a Flashing Don't Walk" for thecross street. Thereafter the sequence of operation proceeds as indicatedin FIG. 3 until such time as the B-extension period is reached. At thispoint, the timing circuits are responsive to an additional element, theadditional element being the number of vehicles passing theintersection. Each vehicle provides for an impulse which only in thiscondition resets the internal timing circuit to zero, i.e., restarts theintercounter would never move from its B-extension" position except forthe fact that an additional overriding timing element, called themaximum timer," is provided to terminate the extension period. Thus, thecounter is moved out of its B-extension position, possibly by themaximum timer. If there is a requirement that the maximum counter go toits termination, a pulse is provided at point 106 (FIG. 2A) which resetsthe vehicle memory circuitry so that in the event there are carsawaiting passage at the intersection, the controller has to go throughanother sequence.

It was noted above that the and" box 14 will provide a stepping voltageor signal to the timing circuits of box 15 upon reception of a signalfrom the vehicle detector 10 or the pedestrian pushbutton 11, providedthat other conditions are right. These other conditions are (I) that thecounter is in a rest position after having passed through Green-lminimum, and (2) a coordination control is properly set. Thiscoordination control correlates the controller to other traffic lightsas will be hereinafter more specifically described.

Describing now the vehicle detector and related memory circuits,reference is made to FIG. 2A. When the vehicle detector 10 is operatedby passage of a vehicle, it combines with the vehicle memory (box 12)which consists of a two st'age bistable multivibrator transistor circuithaving transistors 100 and 101, one stage of which will be on while theother is off. An operation of this transistor circuit will cause aflip-flop reversal of the initial conditions. Under normal conditions,transistor 101 is conducting so that the output at point 102 will be atground zero or ground potential. Transistor 100 will be nonconductingand the voltage at point 103 will be at supply potential, for example,+22 volts, thus shunting the vehicle call indicator 103A. The operationof the vehicle detector l0 grounds the input point for the circuitthrough lead 104 and causes transistor 101 to become nonconducting, thusraising the point 102 to supply voltage logic I" condition. Transistor100 becomes conductive, lowers the voltage at 103, and lights indicator103A. During the extension interval, a voltage is introduced at point orlead 105 so that transistor 101 will again be caused to be conducting soas to lower point 102 to zero. An additional method of settingtransistor [01 to its nonconducting condition is through the maximumrecall circuit which will be described at a later point. The maximumrecall pulse is applied to point 106. A vehicle recall switch 107provides for operation of transistor 100 and consequent placing oftransistor 101 in a nonconducting condition under manual control, duringthe "A" rest position.

Describing now the pedestrian memory circuit, box 13, it will be seenthat this circuit consists essentially of two flip-flop .25 val timingfor the extension period. Thus, theoretically the bistable multivibratorcircuits, one having transistor 108 and 109, and the other transistorsand 111. The second circuit can be denoted as the ped memory auxiliarycircuit. Transistor 108 is normally conducting and 109 nonconducting.The operation of the pedestrian pushbutton 11 sets transistor 108 to anonconducting condition to provide an output at point 112. Transistor109 is connected to the pod call" indicator 113 which will provide avisual indication of the reception ofa pedestrian actuation. During theB-walk period, transistor 108 will be returned to its conductingcondition via line 114. In addition to operation from the pedestrianpushbutton, the transistors 108 and 109 of the first memory circuit maybe operated by a manually operated recall switch 107. The recall switch107 can be in the pedestrian recall position, off position, or a vehiclerecall position. In either of the recall positions, a signal isintroduced during the A-rest interval period which will provide a resultequivalent to pushing the pedestrian button or vehicle detectoractuation and causes recycling of the controller without need of vehicleor pedestrian actuation.

The auxiliary memory circuit including transistors 110 (normallyconducting) and 111 (normally nonconducting) is set to provide apedestrian output signal at point 115 when the following conditionsexist: (I) a pedestrian call at point 112, and (2) the controller timerdevice is in either A-Yellow or A-All Red condition. As a result, apedestrian output signal will be available at point 115. The pedestriansignal output of flip-flop 110, 111 will be reset to zero, for example,by means of the B- Yellow signal introduced at point 116. When there isa pedestrian output signal and the signal circuits are in a B-Walkcondition, and there is a momentary interruption of power which mightcause transistors 110 and 111 to revert to the nonped-output condition,the B-Walk signal introduced at point 117 will tend to hold transistor111 at its conducting condition so as to'hold transistor 110 in anonconducting output condition, or logic l condition. This will allowfor a continuity of the Walk signal condition. If there is no pedestriancall during the A-Yellow and A-Red periods, transistor 111 will remainconducting and provide a Not Ped" signal at point 151 for a purposehereinafter explained.

Describing the "and" circuit of box 14, reference is again made to FIG.2A in which the purpose of the "and" circuit is to remove the counter 16from' the A-Rest position. The counter 16 is removed from A-Restposition by means of a step voltage which is produced at point 170. Thisoutput volt age may be produced by'me ans of a signal originating at theA- Rest 143 (FIG. 2C) output which is transferred to the point 171 ofFIG. 2A. With transistor 108 conducting, however, the voltage availableat 171 is passed through resistor 172, diode 173 and transistor 108 tothe ground. Thus, no step voltage can result. Similarly, ifthere is novehicle call, then the voltage at 171 is transferred through resistor174, diode 175 and transistor 101 to ground. Thus, no voltage can resultin this case at 170. However, if either or both transistors 108 and 101are nonconducting then a signal will go from point 171 through resistor172 and diode 176 to point 170, or 171, resistor 174, diode 177 to point170. In either of these events, the voltage will be transferred to thepoint 178A of the timing circuitry of FIG. 2B. The action at this pointof FIG. 2B is to cooperate with capacitor 154A to drive unijunctiontransistor into conduction, thus providing a pulse at point 156 which isthen transferred through diode 157, to the count pulse output 118 todrive the counter 16 ofFIG. 2C.

In the foregoing discussion of the removal of the counter from theA-Rest position, no note was made of the coordination circuit, thecoordination transistor being 178 of FIG. 2A. With this circuit in use,the transistor 178 is normally driven into conduction by means of supplyvoltage through resistors 179 and 180, thereby connecting point toground and preventing the stepping or removal of the counter 16 from theA-Rest position except at predetermined periods of time coordinated tothe operation of other controllers, such as is used in New York City,for example. A coordination device which is essentially a switchingelement, as shown schematically at 181, operates the circuit. When thisdevice is closed, resistor 179 is grounded and resistor 182, acting fromthe negative source, causes transistor 178 to be cut off. When thisoccurs, the point 170 is no longer grounded and therefore the stepvoltage can pass on to the counter as outlined above.

The timing circuits are shown in FIG. 2B and are essentially RC circuitsin which the value of the series resistance is changed by variablepotentiometers, box 19, to effect timing variation. It will be seen fromFIG. 2D that a different timing is obtainable for each of the intervalsA-minimum, A-rest, A- pedestrian clearance, etc. The charging sourceapplied to each of these stages has essentially the same value and, inaddition, is clamped to a regulated voltage so as to insure that theyare essentially the same, e.g., by means of diode 152 (FIG. 2C). Thesevoltages are fed to the variable timing resistors, e.g., 153, of FIG.2D. Each of the variable timing resistors or potentiometers may be setat a desired value to control the timing for the selected interval.However, it will be noted that only one interval voltage is available ata time and therefore only one voltage at a time is fed to the intervaltiming circuit 154B (FIG. 2B) and used to charge the interval timingcapacitor 154 (FIG. 2B). When the interval timing capacitor 154 reachesa critical voltage, the unijunction transistor 155 (FIG. 28) will fire,causing a negative pulse at point 156 to be produced which can be termedthe count pulse." The count pulse is transferred to point 118 (FIGS. 28and 2C) through diode 157(FIG. 28) so as to cause the counter to advanceone stage. The unijunction transistor 155 will virtually totallydischarge capacitor 154. However, to assure complete discharge ofcapacitor 154 for the 160 is used to operate a monostable multivibrator160A. The output of themonostable multivibrator, consisting oftransistor 158 and 159, is used to operate momentarily an intervaltiming light 161 so thatthe termination of an interval is visuallyindicated. In addition, the output of transistor 158 fed through diode163 and resistor 164 is used to drive transistor 162 into conduction todischarge the interval timing capacitor 154 to zero.

The interval timer, in addition to operating from 154, may also becaused to operate from 154A as aforesaid. The value of 154A is purposelychosen as being quite small so that a rapid step of very short time maybe obtained. The reason for this is to take the counter out of the Restposition as heretofore described.

In addition to the interval timing and step circuits heretoforedescribed, the timing circuitry of box 15 (FIG. 1) also includes amaximum interval timing circuit 180A which is fed from-the FF4 terminalof the counter during the initial and extension period, or the Walk,Walk-clearance, and extension intervals of the controller by gating oftransistors 186 and 187 (FIG. 2B). The current from transistors 186 or187 feeds either through potentiometers 184 or 185 (positioned in box19) depending upon whether other circuitry requires the output to beeither in the maximum 1" or the maximum 2 condition. The voltageavailable throughthe potentiometers 184 and 185is imposed'at point 183to charge capacitor 188. When and if capacitor 188 is charged to thetrigger voltage of the unijunction transistor 189, the unijunctiontransistor will conduct and discharge capacitor 188 to produce anegativegoing pulse at point 190. This pulse is transferred throughdiode 191 to the count pulse lead 118 and through diode 192" to operatethe monostable multivibrator comprised of transistors 193 and 194. Whenthe negative pulse originating.

at 190 is transferred to the count pulse line 118, it will drive thecounter into a succeeding position. At the same time, through 192 itwill cause transistor 193 to become momentarily nonconducting for aperiod fixed by capacitor 195 and associated components. Simultaneously,the indicator lamp 196 will show that multivibrator I93, 194 ischanging'conditions.

A positive-going pulse made available at point 197 will be transferredthrough diode 198 and line 305 to resistor 164 and thence to theinterval timer reset transistor 162'in order to cause any residualvoltage that may be present on capacitor 154 to return to zero so thatsubsequent timing ot'154 will not be in error. In like manner, capacitor188 is reset to zero via line 306 and resistor 164A. Also,simultaneously with the operation of this multivibrator, a pulse isproduced by means of differentiating circuits 199 and 200 and applied tomaximum recall point 106. Point 106 is also shown on FIG. 2A, and itwill be seen that diode 201 on FIG. 2A is so placed that thenegative-going pulse will turn off transistor 101 to register a call inthe circuit 100, 101. It will be seen, too, that the maximum recalltakes place on the trailing edge of the pulse, that is to say, whentransistor 193 returns to its usual conducting condition. This providesa sufficient delay to permit the counter to get to the next position,which removes the counter from the B-extension condition. Thus, therewill be no voltage at point 105 and the negative pulse available at 106will be effective in maintaining the set condition of transistor 100 forrecycling the controller at its next A-Rest position.

The counter or logic circuit of box 16 (FIG. 1) can include a four-stagebinary counter which would ordinarily be capable of 16 counts. Itcomprises circuitry as shown on FIG. 2C and consists of transistors 119and 120 as the first stage; 121 and 122 as the second stage; 123 and 124as the third stage; and 125 and 126 as the fourth stage. Forconvenience, the truc" output of the first stage is called FFl and thefalse output is called F1 1. Similar notation has been adopted forstages 2, 3 and 4. It will be understood that when PM is at 1, W1 is atzero; and when FFT is at l," FF] is at zero. The counter, while it is afour-stage counter, has contained within it a feedback circuit such thatwhen stage 3 reaches a 1" output, it automatically drives stages 1 and 2to a 1" output as well. The sequence of the counter and code gating is'indicated essentially in FlG. 3 where for the first four counterpositions the output results in the usual binary count. The counter isselfdriven from its usual fifth count to the eighth count. A similarresult is provided to drive the counter from the usual 12th positiondirectly to the 16th position of the binary count.

The outputs of the counters are combined in AND circuits to form codegates (Box 17 of FIG. 1) which control the emitter follower transistors150, inclusive (Box 20 of FIG. 1). Thus, transistor 144 will provide anoutput when the counter is in condition where logic 1" is obtained atFFT, FF Z, F73 and W. Thus, the four logic l"s from the last mentionedoutputs of the counter define the A-minimum green position. Otherpositions, such as A-red, A-ped clearance, A-yellow, are similarlydefined by a total of four outputs, one from each counter stage. TheA-All Red condition is merely defined by two gate outputs, namely, FF3as l and FF? as 1,"sincc no position exists that does include FF3 andFF3 which define positions of the controller, other than All Red.

The B Initial position is produced twice inasmuch as the first flip-flopis not represented in the code gate to transistor 150. Therefore, the BInitial will have an output through two successive positions of thecounter. In addition, however, the B Initial is also defined by theoutput from the pedestrian auxiliary memory circuit at point 151 (FIGS.2A and 2C). With a not Ped" output, the controller will go into the BInitial I position. If there were, however, a fPed output (point 115,FIGS. 2A and2C) then the circuitry will drive transistor 147 to providea B-Walk output. This is done as shown in FIG. 2C by means of Ffi, TF2,W and FF4 and the Fed auxiliary memory output 115. In like manner, B-Pedclearance output of transistor 146 would be substituted for B Initial IIby means ofinputs 11s, FF1,FF2,F F3 and FF4.

B-Extension and B-Yellow are provided by transistors 148 and 149,respectively, under the counter conditions as listed in FIG. 3. B-AllRed transistor is similar to A-All- Red transistor 140 in that it onlyrequires two code gatings due to the nonusagc of the interveningpositions between 12" and "I6." It should be apparent that the foregoingmethod provides for dependable operation in the event the feedback loopthat sets FF] and FFZ at l whenever FF3 is set at l should becomeinoperative, because then the All-Red signal will simply be repeatedthree times without causing other malfunction of the controller ordangerous signal conditions to be set up.

The circuits for the solid-state relays making up the relay matrix ofBox 20 (FIG. 1) are also shown on FIG. 2D. These relays provide for aninterconnection of the signal lights to prevent conflicting signalindications such as may endanger the trafiic situation. The combinationof these relays could provide for any signal sequence condition desired,with the exception, of course, of the dual Green which is eliminated bymeans of the interconnections of the relay. The relay matrices may bemade up in any way, but in any event, will depend upon the outputs ofthe gated emitter followers.

If the controller were turned on at random, it would assume a randomposition. This is not consistent with needs for traffic control signalssince the person first setting the controller into operation must beaware of the present traffic flow. Therefore, it can be assumed that thebest position to place the controller into condition would be when thesignals show amber or yellow to the main street and red to the crossstreet. This corresponds in essence to the counter position shown as l100 on FIG. 3. The method of doing this is to preset the counter atturn-on. Referring to FIG. 2C, the transistor 201 will be normally shutoff by means of the negative voltage source and resistors 215 and 216.However, at turn-on, that is, when the signal equipment is first turnedon, the positive voltage applied through diode 207 and capacitor 206 issufiicient to drive transistor 201 into conduction for a short while.This conducting condition is operable through diodes 202, 203, 204 and205 to turn off transistors 119, 121, 124 and 126. This turn-on signalis removed almost immediately since capacitor 206 will be charged up andwill no longer conduct. Under this circumstance, the controller, whilestarted in the Yellow-1 condition, will be released immediately so thatit can go through its normal sequence.

The FIG. 3 sequence indicates that there are discrete steps or intervalsin the controller sequence. The counter illustrated in FIG. 2C is abinary counter which has l6 fundamental conditions. As above set forth,means are provided to change the l6-position counter into a lO-positioncounter. This is done by the following method. When position 05 isreached, the situation is such that the code will be 0010. Under thesecircumstances, resistor 209 (FIG. 2C) is gated by diode 210 since thisis the first time in the sequence that this third stage reaches the 1"position. When this happens, a signal is sent out via diodes 211 and 212to change the condition of the two stages so that they, too, are in thel position. This means that from position 05 the circuitry isimmediately driven into position 08. Similarly, when the circuit reachesposition 013, it is immediately driven into position 016. Diode 213(FIG. 2B) is used to gate this control mechanism from the multivibrator158, 159 so that the main gating can take place only during a change incondition. Also, capacitor 214 is included to delay the application ofthis change until such time as the counter has had sufficient time toreach a static normal condition and, therefore, will be able to respondaccurately and dependably.

Under some circumstances, it is useful for traffic control personnel tobe able to operate the equipment manually, without regard to the presettiming controls. A circuit means for this purpose is shown at 300 inFIG. 28. Operation of the switch 301 provides a voltage to the stop timecircuits at 304, to cause transistors 162 and 162A to be continuallyconductive, thus preventing timing capacitors 154 and 154A from reachingthe discharge potential needed to trigger 155 or 189. Operation of themanual control 302 charges capacitor 307 to a value limited by thevoltage divider 305, 306; which value is insufficient to cause 303 totrigger. When 302 is released, the voltage at the base of 303 is reducedto zero and 307 is enabled to discharge, providing a pulse at 118, whichdrives the counter one position. The circuit described provides a cleanpulse for each opening of the manual control 302.

While an exemplary embodiment of the invention has been illustrated anddescribed, it will be apparent that alterations, changes andmodifications may be made in the specific circuits and/or the componentsthereof without departing from the spirit of the invention, and it isintended to be limited only by the scope of the appended claims.

What I claim is:

I. In a traffic signal controller apparatus comprising,

a plurality of bistable stages cascaded to form a binary counter,

an additional bistable means for providing a walk signal representativeof pedestrian selection of a walk traffic condition signalling a safestreet crossing interval for pedestrians,

means for selectively advancing the count in said binary counter toestablish a sequence of different states of said binary counter binarystages,

and decoding means responsive to each state of said binary counterbinary stages for establishing at least first and second traffic flowconditions,

said decoding means comprising at least in part,

first circuit and gating means responsive to more than one stage of saidbinary counter and the absence of a walk signal for establishing a firsttraffic flow condition permitting a safe street crossing interval forvehicles,

and second circuit and gating means responsive to more than one stage ofsaid binary counter and to the presence of a walk signal from saidadditional bistable means for establishing a second traffic flowcondition permitting a safe street crossing interval for pedestrians.

2. Apparatus as set forth in claim 1 wherein said means for selectivelyadvancing the count in said binary counter comprises means for causingsaid binary counter to step through a first group of counts common toboth said first and second traffic flow conditions, said decoding meansincluding means for establishing a first portion of the traffic flowcondition wherein trafiic movement on a first street stops upon reachingthe last count of said first group of counts.

3. Apparatus as set forth in claim 2 and further comprising means forcausing said binary counter to skip at least one count after said binarycounter reaches the last count of said first group of counts.

4. Apparatus as set forth in claim 3 and further comprising means forcausing said binary counter to step through a second group of countsafter said binary counter has skipped said at least one count, saiddecoding means including means for establishing a second portion of saidfirst traffic flow wherein traffic crossing of said first street ispermitted upon reaching the first count of said second group of countsof said binary counter.

5. Apparatus as set forth in claim 3 and further comprising means forcausing said binary counter to step through a second group of countsafter said binary counter has skipped said at least one count, saiddecoding means including means for establishing a second portion of saidsecond traffic flow condition wherein pedestrian crossing of said firststreet is permitted upon reaching the first count of said second groupof counts of said binary counter.

6. In a traffic signal controller apparatus comprising,

a binary counter having a plurality of bistable stages and at least oneinput count line,

timing circuitry means coupled to said count line for selectivelyadvancing the count in said binary counter to establish a sequence ofdifferent states,

decoding means responsive to each state of said binary counter forestablishing at least a first traffic flow condition pennitting at leastvehicle crossing of a first street and a second traffic flow conditionpermitting at least pedestrian crossing of said first street,

and bistable pedestrian memory means including pedestrian actuable callmeans and having a first state assumed when a pedestrian call isreceived and a second state assumed in the absence of a pedestrian call,

said decoding means comprising at least in part,

first circuit and gating means responsive to at least some of saidbinary counter stages and the absence of a call condition of saidbistable pedestrian memory means for establishing said first trafficflow condition,

and second circuit and gating means responsive to at least some of saidbinary counter stages and a call condition of said bistable pedestrianmemory means for establishing said second traffic flow condition.

7. Apparatus as set forth in claim 6 wherein said first circuit gatingmeans comprises an AND gate having a plurality of inputs coupled from atleast some of said binary counter stages and a single input coupled froma second state output of said bistable pedestrian memory means.

8. Apparatus as set forth in claim 6 wherein said second circuit gatingmeans comprises a pair of AND gates each having a plurality ofdifferently arranged inputs coupled from at least some of said binarycounter stages and a single input coupled from a first state output ofsaid bistable pedestrian memory, said pair of AND gates further havingseparate outputs for providing WALK and PEDESTRIAN CLEARANCE intervals,respectively, to permit pedestrian crossing of said first street.

9. Apparatus as set forth in claim 1 wherein said means for selectivelyadvancing the count in said binary counter comprises means for causingsaid binary counter to step through first and second groups of counts,said decoding means comprising third and fourth circuit gating meanseach responsive to like stages of said binary counter wherein said likestages number less than the total number of stages of said binarycounter, said third circuit gating means responsive to a first conditionof said like stages wherein traffic movement on at least a first streetstops upon reaching the last count of said first group of counts, saidfourth circuit gating means responsive to a second condition of saidlike stages of said binary counter wherein traffic movement on at leasta second street stops upon reaching the last count of said second groupof counts.

1. In a traffic signal controller apparatus comprising, a plurality ofbistable stages cascaded to form a binary counter, an additionalbistable means for providing a walk signal representative of pedestrianselection of a walk traffic condition signalling a safe street crossinginterval for pedestrians, means for selectively advancing the count insaid binary counter to establish a sequence of different states of saidbinary counter binary stages, and decoding means responsive to eachstate of said binary counter binary stages for establishing at leastfirst and second traffic flow conditions, said decoding means comprisingat least in part, first circuit and gating means responsive to more thanone stage of said binary counter and the absence of a walk signal forestablishing a first traffic flow condition permitting a safe streetcrossing interval for vehicles, and second circuit and gating meansresponsive to more than one stage of said binary counter and to thepresence of a walk signal from said additional bistable means forestablishing a second traffic flow condition permitting a safe streetcrossing interval for pedestrians.
 2. Apparatus as set forth in claim 1wherein said means for selectively advancing the count in said binarycounter comprises means for causing said binary counter to step througha first group of counts common to both said first and second trafficflow conditions, said decoding means including means for establishing afirst portion of the traffic flow condition wherein traffic movement ona first street stops upon reaching the last count of said first group ofcounts.
 3. Apparatus as set forth in claim 2 and further comprisingmeans for causing said binary counter to skip at least one count aftersaid binary counter reaches the last count of said first group ofcounts.
 4. Apparatus as set forth in claim 3 and further comprisingmeans for causing said binary counter to step through a second group ofcounts after said binary counter has skipped said at least one count,said decoding means including means for establishing a second portion ofsaid first traffic flow wherein traffic crossing of said first street ispermitted upon reaching the first count of said second group of countsof said binary counter.
 5. Apparatus as set forth in claim 3 and furthercomprising means for causing said binary counter to step through asecond group of counts after said binary counter has skipped said atleast one count, said decoding means including means for establishing asecond portion of said second traffic flow condition wherein pedestriancrossing of said first street is permitted upon reaching the first countof said second group of counts of said binary counter.
 6. In a trafficsignal controller apparatus comprising, a binary counter having aplurality of bistable stages and at least one input count line, timingcircuitry means coupled to said count line for selectively advancing thecount in said binary counter to establish a sequence of differentstates, decoding means responsive to each state of said binary counterfor establishing at least a first traffic flow condition permitting atleast vehicle crosSing of a first street and a second traffic flowcondition permitting at least pedestrian crossing of said first street,and bistable pedestrian memory means including pedestrian actuable callmeans and having a first state assumed when a pedestrian call isreceived and a second state assumed in the absence of a pedestrian call,said decoding means comprising at least in part, first circuit andgating means responsive to at least some of said binary counter stagesand the absence of a call condition of said bistable pedestrian memorymeans for establishing said first traffic flow condition, and secondcircuit and gating means responsive to at least some of said binarycounter stages and a call condition of said bistable pedestrian memorymeans for establishing said second traffic flow condition.
 7. Apparatusas set forth in claim 6 wherein said first circuit gating meanscomprises an AND gate having a plurality of inputs coupled from at leastsome of said binary counter stages and a single input coupled from asecond state output of said bistable pedestrian memory means. 8.Apparatus as set forth in claim 6 wherein said second circuit gatingmeans comprises a pair of AND gates each having a plurality ofdifferently arranged inputs coupled from at least some of said binarycounter stages and a single input coupled from a first state output ofsaid bistable pedestrian memory, said pair of AND gates further havingseparate outputs for providing WALK and PEDESTRIAN CLEARANCE intervals,respectively, to permit pedestrian crossing of said first street. 9.Apparatus as set forth in claim 1 wherein said means for selectivelyadvancing the count in said binary counter comprises means for causingsaid binary counter to step through first and second groups of counts,said decoding means comprising third and fourth circuit gating meanseach responsive to like stages of said binary counter wherein said likestages number less than the total number of stages of said binarycounter, said third circuit gating means responsive to a first conditionof said like stages wherein traffic movement on at least a first streetstops upon reaching the last count of said first group of counts, saidfourth circuit gating means responsive to a second condition of saidlike stages of said binary counter wherein traffic movement on at leasta second street stops upon reaching the last count of said second groupof counts.